Pulse-operated receiver

ABSTRACT

Disclosed is a receiver for a navigation system of the Omega type which operates with pulse-modulated signals. The phase of received and local signals is compared by quantized pulses; phase equalization, commutating gate control, phase tracking, and synchronization of gate patterns with timed-sequence input signals are obtained by pulse insertion into, or deletion from, signal loops which contain phase detecting, sequential signal selecting, and readout control components. Phase coincidence is counted cumulatively and is electromechanically stored. Lane position is recorded by pulse insertion. Components are constructed and interrelated to reduce noise and improve selectivity to enhance the benefits obtained by pulsed operation control.

United States Patent 1 Odams l l PULSE-OPERATED RECEIVER [111 3,875,5185] Apr. 1, 1975 Primary Examiner-Stanley T. Krawczewicz 75 Inventor:Charle E. d ms, Lo d d l l N H S a n on any Attorney, Agent, orF1rm-Robert G. Crooks;

' Jefferson Ehrlich [73] Assignee: American Standard Inc., New York,

NY. 57 ABSTRACT [22] Filed; May 10, 1973 Disclosed is a receiver for anavigation system of the Omega type which operates with pulse-modulatedsig- [211 Appl' nals. The phase of received and local signals is com-Related US. A li ti D t pared by quantized pulses; phase equalization,com- {62] Division ofSer. No. 889,368, Dec. 31, 1969v Pat. No. f gatePhase and f f 3,313'477 zation of gate patterns with timed-sequenceInput s|gnals are obtained by pulse insertin into, or deletion 52 us. Cl328/155, 324/83 FE, 328/134 from, signal loops which contain phasedetectingv 151 int. Cl. H03b 3/04 quemial Signal Selecting. and readoutcontrol p 5 1 Fieid f Search 324 3 2 3 nents. Phase coincidence iscounted cumulatively and is electromechanically stored. Lane position isre- 5 References Cited corded by pulse insertion. Components are con-UNITED STATES PATENTS structed and interrelated to reduce noise andimprove 7 973 870 2/1960 t I 3 FE selectivity to enhance the benefitsobtained by pulsed lguorie a. .t 3.430.234 2/l969 Wright 324/85 comm3.579.128 5/1971 Smith et a! 328/ 3 Claims, 19 Drawing Figures lo Y ZI33 lflc'Y again r-1 raw? PH/fSf I32 xon: WY gasses. WWW;

1/6 #7 n: [AC/1' r0 fOUK fat/71am B'LATERAL p s/razr an:

GflTES PULSE CKT. ,2; [2/ new" 6.5 lg-l uiiiillz'f cau/vmz LOOPsvncunouums I C/IRCUIT Mm was /29 El/4 A22 "GENERMOR fol/1? zt/ws [Ac/lTo RE FE RENCE 2040 rwo(+,-) sflazrinres I26 OSCILLATOR A24 SYNTHESIZERPlPE GENERATOR CHART RECORDER DlSPLAI PHASE DETECTOR SHEET C18? 12 JI LJI L T Q3 gamma Hm ER 5N j mmBz M m3 W 983 NQNQ PULSE-OPERATED RECEIVERThis is a division of application Ser. No. 889,368,

filed Dec. 31, 1969, now issued as U.S. Pat. No. 3,818,477.

BACKGROUND OF THE INVENTION 1. Field of the Invention The inventionrelates to radiowave communication systems (Class 343), and particularlyto transmitting beacons of the isophase type producingpositiondeterminative signals (Subclass 105).

2. Description of the Prior Art The rapid increase in volume and speedof long distance ship and airplane traffic has increased the requirementfor a reliable worldwide navigational system. It has been found thatvery-low-frequency (VLF) signals, e.g., on the order of K I-Iz., havesuitable propagation characteristics in that they are detectable atgreat distances from one transmitting station and they are characterizedespecially by very-high, phase-delay stability, thus, the phase at aparticular position on the earths surface is predictable by use of thesesignals. Therefore, navigation systems operating at these frequenciesand based on phase-comparison technology are particularly useful.Several variations of such systems have been investigated. Installationswhich furnish hyperbolic lines of position defined by phase differ encesof time-shared signals from several transmitting locations arepreferred. The reliability and phase stability of VLF propagation makespossible the use of verylong-range, accurate, position-determiningsignals for establishing a hyperbolic line system wherein position isdefined by the points of phase coincidence of a pair of signals receivedrespectively from each of at least two precisely synchronizedtransmitters. The hyperbolic lines of position are plotted, forinstance, on a navigation chart, to produce grid lines, and these linesare separated by lanes' whose width depends on the wave length of thetransmitted signal. Phase coincidences of a synchronized, wave generatoron the ambulating craft whose position is to be determined with thesignals producing the grid lines traversed by the craft furnish a fixand course trace. In order to obtain a fix, signals must be received andprocessed from at least three transmitting stations. One system of thetype described is the OMEGA Navigation System. The Omega system andother similar systems are described in the literature, for example, inSelected Papers Related to LongRange Radio Navigation presented at theCongress on Long-Range Navigation held in Munich, Germany, during 26-3lAug. 1965 and reprinted by the Omega Implementation Committee for theUnited States Navy Department. U.S. patents classified, as indicatedabove, also deal with this subject matter, for example, U.S. Pat. Nos.2,778,013, 2,855,595, 3,209,356, 3,263,231 and 3,388,397.

All receivers presently used in these navigation systems are known tohave limitations affecting their use. They are bulky, and they aredifficult to operate thereby necessitating the use of skilled, trainedpersonnel. Additionally, the receivers are inaccurate and are not asreliable as they need to be in this application. They are expensive andare not suitable for semiautomatic or automatic operation, thus they arenot suitable for use in modern, high-speed air and space craft.

SUMMARY OF THE INVENTION It is, therefore, an object of the invention toprovide an improved navigation system receiver.

An additional object is to provide a navigation system receiver capableof fixing the position of a craft with a high degree of accuracy.

In the embodiment described, the invention is characterized by the useof pulse-signal or digital circuitry wherever possible, forintercircuitry signal-trains as well as output signals; the circuitryfunctions being defined in terms of pulse insertion and deletion, ofpulse amplitude, duration and position modulation, of pulse quantizing,of pulse multiplexing, and of counting and storing ofinformation-carrying, pulse trains. This characteristic concept isapplied, directly, or indirectly, for its ultimate purpose, to variouscomponents of the navigational system, which comprises a local referenceoscillator, a phase error detector, a selector for separate comparisonof the several received time-shared signals with the local timereference, circuitry for matching the local phase with the phases ofselected, received signals, and tracking apparatus for translating phasedifferences into terms of the hyperbolic grid.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and la are schematic diagramswhich, together with a tabulation contained in the description andreferring to these figures, illustrate the general structure andoperation of the present system in easily comprehensible fashion;

FIG. 2 is a simplified block diagram of the complete system emphasizing,as distinct from FIG. 1, circuitry lines rather than functionalinterrelation; the identify ing numerals of the blocks correspond tothose of FIG. 1; groups of blocks in dotted line frames whichincorporate the above-characterized inventive aspects are marked withcapital letters;

FIGS. 3, 4 and 5 are detailed circuit diagrams of the phase equalizationgroup, within dotted line, frame A; the wiring of the detail circuitryof this group and of the other groups is completely evident from therespective figures, and their description is completed by a tabulationreferring to the numbers marked on these figures and giving the names,ratings, or other identifications of the circuit elements;

FIGS. 6, 6A, 6B, and 7 are detailed circuit diagrams of the signalsegregation group, frame B;

FIG. 8 is a detailed circuit diagram of the cumulative counting group,frame C;

FIG. 9 is a timing diagram illustrating the operation of the storage andcount-out circuitry, group C;

FIG. 10 is a detailed circuit diagram of the comparator and coil driver;

FIG. 11 is a detailed circuit diagram of the lane position recordinggroup, frame D; and

FIGS. I2, 13, 14, IS and 16 are detailed circuit diagrams of theamplifier group, frame F.

DESCRIPTION OF A PREFERRED EMBODIMENT General Outline With reference toFIGS. 1 and la, an operational description of the system as a whole withsome simplifications, will first be presented in the form of atabulation which combines references to the function blocks of FIG. Iwith their operations correlation. The blocks are 3 identified byidentical numerals in both the tabulation and in FIGS. 1 and la.

As mentioned above, four transmitters, with their respective signalsphase-synchronized, are assumed for purposes of the present description.The signals from the respective transmitters are indicated in FIG. 1 ata, 10b, 10c and 10d. As indicated, each transmitter transmits for agiven period of time, a, b, c, d, and the transmitting periods of eachtransmitter is staggered with respect to all other transmitters. FIG. laschematil0 cally represents two hyperbolic lane systems established bytransmitted signal pairs, such as a, b and c, d,

respectively, and forming, when superimposed. a nearly rectilinear grid.While FIG. la shows the plotted signals from the four transmitters 10a,10b, 10c, 10d and their hyperbola axes, it will be understood that thespatial relation of transmitters and grid is grossly distorted, asindicated by the broken axis lines. It should be noted that FIG. 1 andthe tabulation set forth in the following material include only thecomponents necessary to process the signal from one transmitter,although the number of components required for processing all thesignals in a complete system, as described, is indicated by legend.

lnput Output Mark Name from Operation to l 10a Plurality Transmitsynchronized VLF (l0.2 KC) signals in 1 10b (here four) timed sequencefor corresponding receiver l lOc of transchannels I l l mitters ll 1Antenna and I I0 Receiving antenna for l0.2 KC signal, and H Coupleru,b,c,d coupling with amplifier l lZa RF l l l Distributed filter andlimiter amplifier with l 12b Amplifier optimal phase constancy 1122 1l2a Superheterodyne amplifier furnishing sinusoi- 1 l6 Amplifier ll4sdal 6.8 KC signal I23 1 Reference 129 Generates stable pulse train.continuous at Oscillator 2040 KC, for amplifier, timing function withLocal generator and adder subtractors. Feeds into 1 5 local synthesizerH4: which supplies l7 KC signal after division by [20 signal afterdivision by 120 1 l5 Timing Funcl22 Generates commutation pattern forsegregating 1 timed sequence signals a, b. c, d in timed 1 p sequence.Pattern synchronized with patterns of a. b, c. d 125 126 132 [I6 PhaseError l2 Compares signals a, b,c, d with local square I 17 Detector l2lwaves from tracking synthesizers 20. Furnishes DC voltage going from--0.5 to +0.5 volts as phase error goes from to +90 117 Bil l H6Analog-digital converter of DC. phase error Pulse signal into pulses atcorresponding frequenl D cies from zero pps for zero volt to 30 pps for0.5 volt. Pulses corresponding to and volt on corresponding andoutputlines p and n Slim! gales l l Segregate four tracking loops for the fourI1 F r P ir 1 l7 signals a, b, c, d by way of timing signal 125 P" 117signals a, b, c. d by way of timing signal 218" h nn l) from 1 l5 and pand n signals from I 17. Open slightly shorter than a. b.c. d sequencese c.

[19 Adderl 14 Combine p, n pulses from 17 and l 18p. ll8n 120 219Subtractors l18p with continuous pulse train 2040 KC from 1 I4, 319 Four(one llBn inserting or canceling a 2040 KC pulse for M9 per channel)each p, n pulse respectively 120 Tracking 9 Frequency dividers countingdown by a factor 121 220 s h i of 300. Furnish 6.8 KC square waves with129 320 Four (one phases advanced H300 of a cycle for each I30 420 per hfl) pulse added and retarded I I300 for each pulse deleted. Continuous6.8 KC output signal. Once phase lock with 1 l2 is established, 1 l7ceases to furnish p, n pulses. The pulses fed from M7 to I25, I26,measure the phase lead or lag of the signals from l0, quantized at 1/300cycle. 121 Four Long 120 Close the tracking servo loops 19. 20 back toH6 Gates 116. Driven by ll8p. 11811 from 115. synchronized with a. b. c.d Open for full 0, b. c. d

Continued Mark Name Input Operation Output from to I22 Sequential I HiCauses pulses from I24 to be added or deleted I Channel I I4 untilcoincidence is reached between gate Synchroniz- I24 pattern of I I5 anda. b. c. d envelopes from ing Circuit I24 as observed at I33 when 124 ismanually stopped I24 Pipe Manually controlled, furnishes pulses to beGenerator added or subtracted at I22 I2 125 Add Counter l lllp Sum addpulses from l l8 of one channel with I27 Stores l Ilia subtract pulsesfrom 218" of another channel.

Feed into comparator and coil driver I27 I26 Subtract l [Hp Sum subtractpulses from l l8" of one channel I27 Counter l lltn with add pulsesfront I 18p of another channel.

Stores Feed into coils I26.l

I27 Comparator I Prevents counter from being driven in both I275 CoilDriver I26 directions simultaneously I275 Counters I27Electromechanically record continuously the OUTPUT net differenceprovided by I 27. this being the change of one centilane IZK SynthcsiverI I4 Develops 6.8 KC for I29 I29 I23 I29 Loop Digital I20 Detects phasedifference between I I4 and one l [4 Phase preferred (usually thestrongest received] Detector loop of I20 (one of u. h, r', d), to lock II4 to respective sender. in digital terms I30 Display I20 Compare 6.8 KCoutput signals of pairs I9. 20. I3]

Phase Furnish ramps from zero to maximum correspond Detectors ing tophase differences from zero to full cycle I31 Chart I30 Graphicallyrecord the lanes crossings as ()L'TPL'T Recorders lines traversing thechart relatively to a time base I32 Envelope I III? Develops envelopesofa. h. 1, 11 I31 Detector l 28 I33 Envelope I I5 Presents a. h, c. denvelopes and commutation ()L'TPL'T Scope 132 pattern in dual traceagainst same time base to display synchronization In order to facilitatea concise description of the embodiment and to correlate the same to theclaimed structure, subdivision headings have been arranged to identifythe previously mentioned frames," marked with capital letters in FIG. 2.Respective blocks of the Schematic Drawings and frames are marked withnumerals which correspondingly recur in all figures.

Where it is appropriate to the description, interconnections between thevarious components are marked with labels coded to indicate the blocksby their respective numerals and are further labeled by i" for input ando for output, respectively, for example, i 112 is the input terminalfrom block 112, and o 112 is the output terminal to block 112.

A. Phase-Locked Loops Referring to FIGS. 3, 4 and 5 which discloses aphase-locked loop, frame A, including blocks such as 116, 117, 119 and120, and refer additionally to FIGS. 1 and 2 in order to correlate thedescription to the system operation. Each transmitted signal fromstations 10a, 10b, 10c and 10d is tracked in a respective servo loopwhich is adapted to develop a continuous local signal which isphase-locked to the intermitten transmitted signal. For instance, asingle reference oscillator 114 (FIG. 2) provides a local, precision,phase signal for all servo loops. Each respective loop includes acommon. phase-error detector 116 which compares the signal from mixer11% with a corrected, local signal derived from reference oscillator114. The phaseerror detector 116 has a DC output which is positive,negative, or zero depending on the phase difference be tween thecompared signals. This DC output is fed to and controls a bilateralpulse generator 117 which is common to each loop but has two outputlines; one line carrying pulses corresponding to a positive phasedifference, the other line carrying pulses corresponding to a negativephase difference. The two output lines are coupled through commutatinggates, to be fully described under B, 118p, 11811, 218p, 218n, 418p,4l8n, sequentially to each one of four local slave channels including,respectively, an addcr-subtractor 119, 219, 319, 4l9 and a divider 120,220, 320, 420. The function of each adder-subtractor, such as 119, is toadjust the 2040 KC reference oscillator signal, from 114, by eitheradding a pulse for each positive pulse from generator 117, or deleting apulse for each negative pulse from generator 117. The following dividers120, I20, 320, 420 convert the adjusted 2040 KC signal to the 6.8 KCsignal which is to be compared in phaseerror detector 116. Each pulseaddition in addersubtractor 119 changes the phase of the 2040 KC signalby 360. After division by a factor of 300 by divider 120, the net effecton the 6.8 KC comparison signal is to make a phase change of 12 or l/300cycle therein.

As the receiver is moved with relation to the transmitting stations. thephase of the received signal changes, and the phase of the localcomparison signal must be changed to maintain coincidence. The pulseswhich correct the phase of the local comparison signal serve as ameasure of change of phase, and therefore of receiver change of positionwith respect to the respective transmitting stations. By properlycomparing the number of positive and negative pulses produced in phasetracking a pair of transmitting stations, as will be hereinafterexplained with reference to frame C, it is possible to determine wherethe receiver lies within the lanes and centilanes (FIG. la) which arecharacteristic of the Omega navigation system.

I. Phase-Error Detector 116 (FIG. 3)

Phase-error detector 116 compares the 6.8 KC input signal, derived inmixer ll2b from the transmitting station 102 KC signals a, b, c, d, withthe corrected 6.8 KC comparison signal from the appropriate localchannel, as follows. Transistor Qla constitutes an emitter followeramplifier for the signal received at input 1' 112b. This signal is fedthrough the two diodes Dla and D20, connected in push-pull arrangement,through balanced transformer Tla and capacitor C30. Transistor 02aconstitutes an emitter follower amplifier for the reference signal fromterminal i 121, which is fed as a singleended signal into both diodesD1a and D2a through the transformer center-tap. The diodes D10 and D20act as gates controlled by the reference signal, and operate to passalternate sections of the 6.8 KC input signal. Since each tracking loopor channel is gated to correct phase every time its associatedtransmitter signal is received (approximately once every ten seconds inconventional Omega practice), the phase detector 116 will make smallcorrections and operate near zero output.

The signal passed by diodes D10 and D2a is integrated by capacitor C4ato remove high-frequency AC components, and is then fed to anoperational integrater including amplifier ARla having feedbackcomponents R9a, C50, R8a. The operational integrater reduces the highfrequency components of the phaseerror signal and provides sufficient DCgain to negate the effects of offsets caused by drift which isassociated with a bilateral pulse generator of the type described below.

The servo loop gain is determined by the DC gain of the phase-errordetector and the time constant of the bilateral pulse generator. Thisdesign provides a noisefree, phase-tracking velocity of approximately3.6 microseconds per second or a bandwidth in this instance of 0.036cycles, approximately. The performance of this noise free bandwidth,examined in an input signal to noise ratio of 1/10 in a 100 Hzbandwidth, yields a microsecond lag-angle of a baseline velocity of 35knots, which is deemed adequate for current vehicle movementrequirements. The output ofthe phase-error detector 116 is a DC voltagewhich is either positive, negative or zero, and of variable magnitude,depending on the phase relationship of the compared signals. The DCsignal appears at terminal 0 117.

2. Bilateral Pulse-Generator 117 (FIG. 4).

The DC output voltage from the phase-error detector 116 is convertedinto a series of pulses whose frequency depends on the magnitude of theDC voltage. Depending on the polarity ofthe DC voltage, the pulses aresegregated to output terminal 0 Sn (negative polarity) or outputterminal 0 118p (positive polarity).

The DC input from terminal i 116 is integrated by operational amplifierARZa to produce a signal ramp which will be either positive or negative,depending on the polarity of the voltage. The steepness of the ramp isdetermined by the magnitude of the voltage. Across integrating amplifierAR2a are connected two pairs of complementary transistors O3a-O4a andQ5aQ6a connected regeneratively to form an artificial fourlayer diode.When the voltage across either pair reaches the breakdown voltage, thepair conducts, discharging the integrating capacitor C9a. As a result, apositive or negative saw-tooth wave, whose polarity and frequency dependon the input voltage, is produced at the output ofoperational amplifierARZa. The saw-tooth wave is differentiated by capacitor C 16a to producea series of positive or negative pulses. These pulses are amplifiedthrough transistor 07a, and segregated by the pulse separator formed bytransistors 08a and 09a. Transistor 08a is biased to be sensitive onlyto the positive pulses which thus appear as positive pulses at outputterminal 0 11811. Transistor 09a is biased to be sensitive only tonegative pulses which are then inverted by transistor Ql0a to appear aspositive pulses at output terminal 0 118p. The frequency of the pulsesdepends on the input voltage magnitude, which is dependent on themagnitude of the phase difference between compared signals. The pulsefrequency, in the examples shown, is on the order of 0 to 60 cycles persecond.

3. Input or Short Gates 118a, l18n (FIG. 5)

As shown in FIG. 2, the phase-error detector 116 and the bilateral pulsegenerator 117 serve all of the local tracking-channels, being connectedsequentially to the channels by input gates 118p and 118n, etc. andoutput gates 121, etc. The input gates 118p, 11811 are shown in FIG. 5.They are simultaneously gated by a signal at i to pass pulses from thebilateral pulse generator 117 to the adder-subtractor 119 and to the addand subtract counter storage 125 and 126. Besides the shared detector116 and generator 117, each local tracking channel has connected to thereference oscillator 114 its own separate adder-subtractor 119, 219,etc. and tracking synthesizer 120, 220, etc., a construction of which isdescribed in detail below for a single channel, the other channelshaving identical components.

4. Adder-subtractor 119 (FIG. 5). The addersubtractor 119 uses thepulses produced by bilateral pulse generator 117 to adjust the phase ofthe local 6.8 KC reference signal which is compared to the incomingsignal in phase-error detector 116. The addersubtractor 119,accordingly, has inputs from the bilateral pulse generator 117 (throughgates 118;), 11811), and it moreover has an input i 114 from the 2040 KClocal reference oscillator 114. The output at terminal 0 is a 2040 KCsignal with pulse additions corresponding in number to pulses at theinput i 118p, and pulse deletions corresponding in number to pulses atinput 2' 118:1. This modified 2040 KC signal is then divided downwardlyby a factor of 300 in the tracking synthesizer 120 to produce aphase-corrected 6.8 KC signal suitable for comparison in the phase-errordetector 116.

The operation of the adder-subtractor 119 is as follows. For simplicity,the add and subtract functions will be taken separately. An add pulsethrough gate 118p triggers an Eccles-Jordan flip-flop 250, which opensgate 26a. The opening of gate Z611 permits the negative-going portion ofthe 2040 KC signal to trigger monostable multivibrator 28a to produce a100 nanosecond delay. At the conclusion of this 100 nanosecond delay,monostable multivibrator 29a is triggered and produces a second 100nanosecond delay pulse which is additively combined with the 2040 KCsignal in gate 212a, the 2040 KC signal with inserted pulse then passingthrough gate 214a to output terminals 120. The signal which starts thefirst multivibrator Z80, also resets flip-flop ZSa through gate Z4a, toreturn the components to starting condition so that a second add pulsewill produce the same result.

Subtract pulses through gate 1l8n trigger a separate flip-flop ZlSawhich opens gate Z17a to permit the 2040 KC signal to trigger monostablemultivibrator Zl5a. Monostable multivibrator ZlSa has a period ofapproximately 600 nanoseconds, which is slightly greater than the lengthof a single 2040 KC cycle. This 600 nanoseconds pulse is then used toinhibit gate Zl4a to interrupt the 2040 KC pulse train for this lengthof time, thereby eliminating one pulse. The pulse train, with deletion,appears at output 0 120. The pulse which triggers multivibrators ZlSaalso resets flip-flop ZlSa through gate Z19a so that original conditionsare again established and the process can repeat.

The signal at output terminal 0 120 is thus a 2040 KC signal which hasits phase advanced 360 for each pulse at input 1' 118p, and retarded 360for each pulse at input i I18n.

5. Tracking Synthesizer 120 (FIGS. 1, 2).

Tracking synthesizer 120 counts down, or divides, the 2040 KC,phase-adjusted signal appearing at terminal 0 120 of theadder-subtractor 119, by a factor of 300. The resulting signal is thelocal 6.8 KC comparison signal which has its phase advanced or retardedl.2 for each pulse generated by the bilateral pulse gen erator 117 andinserted or deleted from the 2040 KC reference signal inadder-subtractor 119. This phase corrected 6.8 KC tracking signal isthen commutatecl through gate 121 to be compared in phase-error detector116 with the received signal from the station transmitting at that time.During the time that a local tracking channel is gated into the phasedetecting circuit, errors of phase coincidence are being corrected bythe servo mechanism which has been described. Because of the discretenature of the phase correction signal, the reference 6.8 KC signal movesback and forth across the zero-error position by steps of 1.2, with theresult that the actual RMS error is less by a factor of 2. During thetime that a tracking channel is gated out of circuit with the receivedsignal (9 out of every 10 seconds in ordinary Omega practice), the 6.8KC comparison signal continues at the phase last established. The pulsesproduced by the bilateral pulse generator 117 are then interpreted asincremental changes of position of the receiver with respect to any onetransmitter. By combining pulses from two tracking channels, it ispossible to interpret the pulses as changes of position within thehyperbolic lanes of phase coincidence between the signals of the twotransmitters so tracked. Since 300 pulses of one sense or would resultin complete phase change of one cycle of the local 6.8 tracking signal,it follows that each single pulse represents H300 of a lane.

The numerals 1 to in FIGS. 3 to 5 represent in conventional manner theterminal numbers of the respective integrated circuit devices to whichthey are applied. The numerals 0 and 1 within the flip-flop symbolsindicate the output states in conventional manner.

The nature and electrical connections of the elements of each of thecircuit components contained in frame A (with the exception of theconventional counter at are clearly shown in FIGS. 3 to 5.

B. Commutator Circuitry Selection of the appropriate channel (119, 120to 419, 420) is carried out by means of eight input gates 118p, 118n to418p, 41814 and four output gates 121 to 421 in response to a gatingpattern signal generated by timing function generator 115. Generator 115produces a gate pattern which is synchronized with the incoming Omegaenvelope pattern by slewing circuitry comprising a manually controlledpulse generator 124 which, by manual selection, provides pulses to beadded or subtracted in a synchronizing circuit 122. The synchronizingcircuit 122 operates similarly to the adder-subtractor 119 to advance orretard the phase of a clock signal derived from the local referenceoscillator 114. The clock signal, with its phase advanced or retardedfor synchronization, operates shift registers in the timing functiongenerator 115, which in turn controls the opening and closing of inputgates 118p, ll8n to 418p, 418n (illustrated in FIG. 5) and output gates121 to 421 (illustrated in FIG. 6).

In addition to providing a gating signal to commutate the local trackingchannels, the timing function generator 115 provides a clock with 10 ppsand a sequential, resetting signal for the add-and-subtract counterstorage 125, 126, which will be explained in greater detail withreference to frame C.

1. Timing Function Generator (FIG. 7)

The timing function generator consists of a decade divider (FIG. 6)which provides a ten pulse-per-second signal, slewable in real time asdescribed in the material that follows, a counter and decoder (FIG. 6aoperating at a 10 Hz rate, and a shift register (FIG. 7) which provideslong and short gates used to open and close gates 119p, 1181! to 418p,418n (FIG. 5) and output gates 121 to 421 (FIG. 6).

Pulses from the decade divider (FIG. 6) are fed at a 10 Hz rate to i 115of FIG. 6a, the basic time counter and decoder. Z16, Z12, Z8 and Z4 arebinaries connected for a 10 count. The output of Z4 drives Z1, Z5, Z9,and Z13 which constitute a second, similarly connected counter. Selectedoutputs from the binary stages are combined in gates Z18 and Z togenerate a zero pulse corresponding to the initiation of the internallygenerated Omega timing cycle, i.e. one pulse is generated for each 10second interval.

The binary outputs are also combined thru several gates and collected inZ18 to generate 8 pulses during the 10 second interval, each oneoccuring at a time corresponding to the end of the short gate interval.These pulses at 0200 (FIG. 6a) are fed to the sampling counter anddecoder (FIG. 6b) to i 200. The output of Z3d sets binary Z6 to enablegate Zl0c. Z10c and Zl0b pass the 10 Hz pulse train which appears at i115 into Z4, Z8 and Z12, a three-stage binary counter. These stagescount at a 10 Hz rate until a digital "six is generated in Z3b whichputs out a pulse actuating Z1, a one shot multivibrator whose outputresets binaries Z4, Z8 and 212 to the zero state and in addition resetsZ6, thereby inhibiting Z10c and stopping the 10 Hz input until the nextpulse occurs at i 115. Outputs from the binary counters are combined in27a and 23 a for a digital number corresponding to a one" and a *five"respectively which set and reset binary Z2. The output of binary Z2corresponds timewise to the short gate signals previously mentioned.

Outputs from the binary counters are further combined in Z70 for abinary number three. This three" is combined with the Hz clock in 210ato provide a synchronous pulse at the exact time to initiate the longgates previously mentioned. This pulse line is fed out through 210d toconnection 0202 to the long-gate shift register (FIGS. 6 and 7). Otherdigital numbers are decoded in 213a, Z13b, Zllb, Z110 and Z1 la. Two ofthese are combined with long gates from the long gate shift register fedin on Z14b, pin i 203 and 2140, pin 1' 204 to generate discrete pulsesbetween the third and fourth Omega transmission segments which are usedalong with the Zero pulse previously mentioned to initiate count outoperation in 125 & 126, 225 & 226, and 325 and 326 of FIG. 2 at discreteintervals during the IQ second timing cycle.

A reset pulse corresponding to the zero" pulse generated in the basictime counter and decoder feeds the long gate shift register (FIGS. 6 and7) and resets the shift register comprising Z8, Z4, Z3, Z7, Z6, Z2, Z1,and Z5, once every 10 second interval. The drive pulse, corresponding tothe binary 3" described in the sampling counter and decoder shifts theregister one stage for each input, thereby generating a pulse on each ofthe eight buffered output lines provided by 212b, 212d, Z1 lb, Z150,215d, Z140, 214d and Z1 la in proper time sequence. These pulses are thelong gates referred to earlier.

The output of each stage of the shift register is in addition fed togates Z120, Z110, 215b, 210b, Z100, Z14b, 29b, and Z90. During each longgate signal, these gates are enabled and act to separate the short gatesignals heretofore developed on one line as described in the samplingcounter and decoder and to provide separate short gate outputs asrequired to operate gates 121 to 421 (FIG. 6).

2. Pulse Generator 124 (FIG. 6).

Pulse generator 124 is a conventional relaxation oscillator employing aunijunction transistor Qlb. The pulse generator 124 operates only whenswitch Slb is closed manually to bias the circuit into oscillation.

By means of switch 82b, the output of pulse generator 124 can beconnected either to time-advancing input i 124p or to time-retardinginput i 124n of the synchronizing circuit 124.

3. Synchronizing Circuit 122 (FIG. 6)

Synchronizing circuit 122 has an input 1 1145 which accepts a 17 KCreference signal derived from the local oscillator 114. This 17 KCsignal is divided by I70 in divider 122d to produce a pulse train of lOOpps which, as modified in a manner now to be explained, appears atoutput terminal 0 115 to run the shift registers in the timing functiongenerator 115. The I00 pps pulse train and the resulting gate pattern isslowed down or hurried up by the addition or deletion of pulses frompulse generator 124 which pulses are manually selected to be appliedeither to the time advancing input i 124p or the time-retarding input i124n. A pulse appearing at input 1' 124p is treated as follows:

A pulse appearing at l24p sets flip-flops Z8b enabling flip-flop 2101)thru gates which are enabled by either 24b or Zb. The next I00 ppssignal occurring at the output of Zlb operates to set flip-flop 21012.The output of 21% enables gate 26b to pass one pps-pulse to initiate twodelay one -shot multiocrotors Z181: and Z191). The output of 21% isdelayed by 21805 until approximately midway between the first and secondsequential 100 pps outputs from Zlb at which time it generates a narrowpulse which is inserted in the 100 pps train by action of gate 22b.

The change in state of flip-flop 2101; is led to set flipflop 29b whichinhibits gate 25b through gates 24b or 21519. The second sequential 100pps output from Alb resets 21% to its original state inhibiting gate 26band returning the circuit to rest until the next pulse on line 0 124pchanges the state of flip-flop 28b.

Similarly, a pulse appearing at the retard input i 12411 is treated asfollows:

A pulse appearing at 124a sets flip-flop Z12b, thus enabling flip-flopZ14b thru gates Z176, which is in turn enabled by either gate Z1 lb orZ16b. The next following I00 pps at the output of 2212 sets flip-flopZ14b, thereby inhibiting gate 23b, and changing the state of 22% toinhibit gate Z176 thru either gate Z116 or gate Zl6b. The secondsequential 100 pps pulse at the output of Z2b resets Z116 which enablesgate 23b and the circuit is at rest condition, having deleted one pulsein the 100 pps train appearing at the output of gate 23b.

Correspondence between the station transmission envelope pattern (a, b,c, d of FIG. 1) and the gate pattern of timing function generator isachieved by the foregoing synchronization circuit. This circuitessentially serves to phase shift the 10-second cycle of the timingfunction generators gating pattern, relative to the time baseestablished by the reference oscillator 114. This is accomplished byinserting extra pulses in. or deleting some of the normal pulses from,the 100 pps train derived from the reference oscillator 114. Since thereference oscillator 114 is phase-locked to one of the received Omegasignals (see description of frame E below), the gating pattern can bemade to coincide, within 1] 100 of a second, to the Omega signal patternas received.

Synchronism can be observed and verified with oscilloscope 133 (FIG. 2).The oscilloscope 133 provides a dual trace for comparison purposes,i.e., one trace being provided by the envelope of the received Omegasignal (developed in envelope detector 132) and the other trace beingprovided by the gate pattern of the timing function generator 115 whichalso provides the sweep. By comparing the two traces, visual observationof synchronism is possible. Other means for observing and verifyingsynchronization are available: For example, a pair of lights energizedrespectively by the gating pattern and by the received Omega signalenvelope will show synchronizationIOr, by way of another example, ameter comparing one channel's envelope with the gate pattern thereforwill show synchronism.

A stop-start switch 83b permits the clock pulse-train, fed to timingfunction generator 115, to be interrupted. When on stop," the switchalso resets at input i 83b (FIG. 7) the shift registers to zero in thetiming function generator. Thus, switching switch 83b, set to start,will initiate the gate sequence on the next clock pulse.

C. Digital Position Display The pulses which are inserted or deleted tocorrect phase in the local tracking channels provide the informationused by the circuitry of frame C for a numberical readout of position interms of lanes and centilanes. These pulses are stored in acounter-register as they are generated, and then periodicallytransferred to the electro-mechanical counters 127.5, 227.5 or 327.5.Each electro-mechanical counter is adapted to display decimally theposition of the receiver, expressed in lanes and centilanes, in relationto a pair of transmitting stations. Usual Omega practice assigns anumber to each of the hyperbolic lines of phase coincidence between apair of transmitting stations and identifies the interline regions aslanes. A centilane is, accordingly, a distance equal to one hundredth ofthe distance between the two lines which the receiver identifies. Afterthe lane and the centilane count is initially set into one of theelectro-mechanical counters, such as 127.5, a change of position of thereceiver, producing phasecorrective pulses in generator 117, isindicated in the following manner. For simplicity, there will bedescribed only the circuitry necessary for handling two transmittingstations, such as a, 10b (FIGS. 1, 1 a) which comprises counter-storage125 and 126, comparator and driver 127, and electro-mechanical counter127.5. Circuitry identical to that of 127.5 is associated with counters227.5 and 327.5, which may, for example, display position with respectto transmitting stations 10b, 100 and 10d, respectively.

Operation of the circuitry blocks 125, 126 and 127 is more easilyunderstood by first considering the arith metic operations to beperformed therein. Briefly, block 125 adds pulses representing positivephase changes in one channel to pulses representing negative phasechanges in a second channel. Block 126 adds pulses representing negativephase change in the one channel to pulses representing positive phasechange in the second channel. The pulse total of block 125 is applied tothe electro-mechanical counter 127.5 in a sense opposite to the pulsetotal from block 126 to obtain the difference between the two numbers oftotal pulses. This difference represents, in pulse terms normalized tocentilanes, the net change of phase at the receiver of the one channel'stransmitting station with respect to the second channels transmittingstation.

1. Counter-storage 125 (FIG. 8).

The storage circuit 125 of FIG. 8 has inputs i 118;) and i 2l8n from therespective short gates, pulses from which are added in gate Z10. Thepulses from the two inputs never coincide to give a false count, sincethe gates 118p and 218n, associated with different channels, are openedsequentially and never simultaneously. As noted above, each pulseinserted or deleted to correct phase represents [/300 of a cycle ofphase change. To obtain a signal whose pulses each represent onecentilane, the input pulses are therefore divided by three in thecircuit formed by Z and Z30. These pulses in turn are applied to abinary count-up register formed by elements Z40, Z50, Z60 and Z70, whichregister has a counting capacity of l6.

The storage circuit 125 further has an input 1' 222 from thesynchronizing circuit 122, as mentioned above, which feeds its 100 ppspulse train to a transfer pulse generator ll5b and a clock pulsegenerator 115a, both of which are actually part of timing functiongenerator 115 referred to above. The transfer pulse generator 1151:delivers a pulse to the pairs of storage circuits 125, 126; 225, 226;325, 326 to instigate the readout process. The pulses are delivered tothe pair in sequence to reduce the power requirements of the receiver,but they are sent simultaneously to both storage circuits forming onepair, such as 125, 126. The clock pulse generator a divides the I00 ppssignal by l0 to produce a 10 pps clock-pulse train.

When a transfer pulse is delivered to the storage circuit 125, it opensgates 290 through Z to transfer the count in the count-up register to asecond register comprised of Z190 through Z220. As the circuitconnections show, the transfer is of the conjugate of the number ofaccumulated pulses in the count-up register. For example, if thecount-up register contained the binary number OOl 1, this would betransferred as its conjugate N00 to the count-down register.

The transfer pulse, in addition to causing the conjugate transfer of thestored-up number of pulses, also triggers a delay component Z250 whichresets the count-up register to 0000 to begin counting anew.

The transfer pulse furthermore latches Z230 into a state enabling gateZ180 to pass to the count-down register the 5 pps signal derived bydividing the 10 pps clock signal from 1150 in binary Z170. The 5 ppssignal through gate Z180 at o 127 passes to comparator and coil driveroutput 127 (FIG. 9) and also is applied to the count-down register. Whenenough pulses have been applied to the count-down register to increasethe count (from the transferred conjugate value) to 1111, the gate 2240is activated and unlatched to disable Z180 so that no more pulses willpass to the comparator and coil driver 127 until the next transfer pulsefrom 11511 is applied.

From the foregoing it is readily seen that the storage and count-outcircuit 125 functions broadly as follows. The input pulses are dividedby three and stored in a count-up register until a transfer pulse causesthe count to be transferred as its conjugate to a count-down register.The count-up register is immediately reset so that it will keep countingpulses generated in 117. The transfer pulse also enables a cloclepulsetrain to deplete the count-down register, at the end of which thecircuitry is reset to its initial condition.

FIG. 9 is a timing diagram depicting certain wave forms during a typicall0 second interval of operation of storage and count-out 125, FIG. 8,circuit. The diagram shows five pulses entering this circuit at input 1'118p during its short gate and four pulses entering the circuit at inputi 218n during its short gate. This total of nine pulses is divided bythree, as can be seen at the Z30 output wave form. This number iscounted into the register composed of Z40, Z50, Z60, and Z70 as shown bythe output wave form of FIG. 9. At the end of the ten second interval atransfer pulse from reset generator l15b shifts the conjugate of thiscount into the register comprised of Z190, Z200, Z210, and Z220. In thisembodiment, in which the total pulse input is nine in the 10 secondinterval, the count-up register reads OOl l (or 3) and the transfer tothe count-down register is made as 1100. Immediately following transfer,the count-up register is reset to 0000 by a pulse at the output of Z250,to make it ready to resume counting during the next interval. Binary Zaccepts l0 pps and provides the 5 pps signal which appears at the outputof Z when that device is enabled by a change of state at the output ofZ240. Z240 assumes one state enabling Z180 whenever any count not 1 l ll is present in the count-down register. The output of the enabled Z180counts out the count-down register and provides the signal ultimatelyfed to terminal 0 127 and to the

1. A control system having a matching means for matching the phase oflocal signal generator output pulses to the phase of control signalpulses including means for defining phase differences in terms ofdiscrete pulses generated only during the presence of said phasedifferences, the number of pulses representing the respective phasedifferences, said phasedifference defining means comprising an input, asawtooth-wave, signal generator which has its output frequencycontrolled by the magnitude of a control voltage at said input, and thepolarity of the output sawtooth-wave controlled by the polarity of saidcontrol voltage, differentiator means for said output sawtoothwavesignal for producing pulses of corresponding frequency and polarity, andseparating means for directing pulses of one polarity to a first pointand pulses of the other polarity to a second point, wherein the localsignal pulses have a frequency which is an integral multiple of thefrequency of the transmitted signals applied to said matching means andwherein said matching means comprises for inserting and deleting saidphase difference defining pulses into and from said local signal pulsesrespectively depending on the sense of the phase difference and meansfor frequency dividing said local signal pulses with insertions anddeletions by said integral multiple so as to obtain a phase-adjustedsignal at the transmitted signal frequency to compare therewith forphase difference, thereby providing a phase adjusted comparison signal.2. The system according to claim 1 wherein said separating meanscomprises a first amplifier biased to respond only to pulses of said onepolarity and having its output at said first point, and a secondamplifier biased to respond only to pulses of said other polarity andhaving its output at said second point.
 3. The system according to claim1 wherein said matching means further includes phase-detector meansresponsive to the phase difference between said phase-adjustedcomparison signal and said transmitted signal, and wherein saidphase-difference-defining means is responsive to said phase-detectormeans.